pulp-platform / axi_slice
Pipelines the AXI path with FIFOs
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Pipelines the AXI path with FIFOs
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
[UNRELEASED] FP div/sqrt unit for transprecision
open-source Ethenet media access controller for Ariane on Genesys-2
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
AXI X-Bar
SystemVerilog modules and classes commonly used for verification
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Simple single-port AXI memory interface
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Common SystemVerilog components
Generic Register Interface (contains various adatpers)
Lean but mean RISC-V system!
AXI Adapter(s) for RISC-V Atomic Operations
RISC-V Debug Support for our PULP RISC-V Cores
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
HW Design Collateral for Caliptra RoT IP
Architecture Labs with CVA6
OpenTitan: Open source silicon root of trust