Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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52 views
Ideas for a project combining arduino and FPGA [closed]
I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
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2answers
48 views
always statement inside case in Verilog
I am beginner in Verilog. So my question may seem easy to you, but I have difficulty in understanding structure of Verilog.
I have one module which works in two modes: read and write. In write mode, ...
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1answer
66 views
Does case satements inside for loop work in verilog?
I am doing a code for radix-4 booth encoding for 8*8 multiplication. The logic is correct and there are no errors or warning. The output am getting is totally unrelated. i have posted the code below
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3answers
64 views
Can someone help me complete this Verilog code for this sequential circuit?
I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
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2answers
62 views
Flip signal values in verilog simulation
I use "force" command in modelsim to force an internal signal to a specific value (not primary inputs). Sometimes, the value I force is the same as the original value.
Is there any command that can ...
1
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1answer
46 views
Question about forcing verilog netlist signals in simulation
I am using ModelSim to simulate a design with verilog netlist and verilog RTL.
My verilog design hierarchy is like this:
tb instantiates ...
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2answers
58 views
Creating SRAM array digitally using Verilog
As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic ...
4
votes
2answers
122 views
Trouble with VGA Controller on CPLD
What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog.
The Problem
I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 ...
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1answer
45 views
Verilog: including one module in another module
I am beginner in Verilog. So I am confused in coding in Verilog. Can I use one module in another module?
...
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39 views
Moving from schematic-based to HDL-based logic design [closed]
I'm a Computer Engineering student (among other things), but most of my prior exposure to logic has conditioned me to think in terms of gates, FFs/latches, and larger functional blocks being wired ...
1
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3answers
48 views
Verilog Netlist format with “\”
After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean.
RTL compiler gives me:
...
1
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1answer
52 views
VerilogIn and Spice out in Cadence or Synopsys
I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out in Cadence. How does this process actually work? What are the ...
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2answers
67 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
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2answers
103 views
Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
4
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1answer
91 views
Difference between @* and @(*) in verilog
What is the difference between always @* and always @(*) in verilog?
2
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1answer
95 views
How to find the critical path delay of a big combinational block
I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
2
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1answer
95 views
What does non-combinational area represent in synopsys design compiler
I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
0
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2answers
141 views
Altera DE1 seven segment display
What I am trying to do is, I want to use Key 0 as a upcounter and key 1 as a downcounter in the same program. I can do that separately. So, when enable is triggered, pressing key 0 will increase the ...
0
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1answer
101 views
Problem initializing Xilinx BRAM
A while ago I added a feature to GNU binutils to convert files to verilog mem files, suitable for reading with $readmemh. The output is very close to what you might get with xilinx's data2mem ...
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2answers
87 views
when do we use disable statement in verilog? is it possible to disable a block outside that block?
I want to disable a block by using an if condition outside that block. I am getting error:
UNEXPECTED DISABLE EXPECTING ASSERT
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2answers
87 views
Nonblocking simultaneous assignments to wires and registers in Verilog
I am interested to write Verilog module which simultaneously will update several outputs Something like following code, makes 3 operations at the same time (clk 10):
...
1
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2answers
67 views
Execute module one after another using flag status
I want to execute 2 modules, one after another using one flag signal
What changes do I have to do in code below to the modules. I have used delay_4 and multiply.
...
1
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1answer
106 views
Verilog output port is high impedance (Z) when driven by a sub module
I'm writing code for shifting 4-bit using carry flag for generating delay using instantiating but when I'm instantiating in top module output of top module temp1 ...
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1answer
97 views
I am not able to instantiate sub modules inside always block
I am designing a floating point unit in verilog. I have designed separate adder, shifter and multiplier modules in verilog. I want to call all these modules and make a single main module. I am not ...
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2answers
128 views
How to give a 2-D array as output of a function in Verilog?
I have to write a code to generate partial products for a 53*53 radix four booth multiplication. I declared a function as shown below; it is showing the error message ...
2
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3answers
128 views
Open Source verilog synthesizer
I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
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1answer
65 views
Inputs are are not able to force to DUT in Testbench
I have written tb in verilog. My testbench inputs are going at high impedance i.e. zz. My dut is not able to force stimulus.Please help me as I m not able detect the problem in my testbench.
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2answers
191 views
How to Add the Xilinx Library to Modelsim
I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
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1answer
58 views
Test_bench in Verilog using Task
I have written testbench in verilog. All the test cases define in task works independently well but when I try to run both task then it give proper output for 1st task in task_operation but not for ...
0
votes
1answer
72 views
How can I detect a pulse from a device with the AC'97 component of a Xilinx Atlys board?
I have a digital device which transmits rapid pulses over a 3.5mm audio cable, indicating that some event has occurred. I want to connect that device to my 3.5mm line in jack on my Atlys board and ...
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2answers
78 views
What do square brackets represent in verilog?
Can anybody help? I know it must be very simple but I am still confused with the following:
M41_1(input0[1],input1[1],input2[1],input3[1],sel0,sel1,out[1]);
What do the numbers in the square ...
2
votes
2answers
249 views
MUX verilog code
Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.
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2
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3answers
80 views
What is the mechanism behind RO or WO and WR registers?
In embedded systems you have read only and write only registers. How are the two type distinguished in the netlist? I can not understand how one build a flop which you can only write and not read ...
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1answer
137 views
Verilog interfacing with C#
Right now, I am taking a course on Verilog HDL, however, our instructor gave us a machine problem wherein we are required to implement a program using verilog while having C# as our main gui. The ...
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4answers
259 views
How to think while working with VHDL or Verilog
All of my experience belong to general purpose programming languages e.g; c/c++ etc where each instructions are executed one after the other but it seems in VHDL/Verilog, all the instructions are ...
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33 views
Error generating simulation file: ldbanno: design file _map.ncd not found
This is what I am trying to simulate using Active HDL in Lattice Diamond
module andd(a,b,c);
input a,b;
output c;
assign c=a&b;
endmodule
When I am ...
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1answer
86 views
Dump verilog array in gtkwave
Is there a way to dump the memory in verilog using vcd dump?
Since now i have written this:
...
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1answer
94 views
Error :4:1 multiplexer
I am getting compiling error while on 2'b100 as it says that Bounds of part-select into 'mux_out' are reversed. Is this the right way to do ?
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1answer
90 views
Data transfer from Latch to PIPO
This program is in Verilog and simulating on Modelsim. I am trying to transfer 48 bits data from 192 bits latch to Parallel in Parallel Out (Register) in 4 slots.
I am not getting output at PIPO. ...
2
votes
3answers
88 views
View more than 100 worst-case paths in Quartus II
I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
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2answers
298 views
Clock Period using Verilog code
I want to calculate time period by using Verilog code. Is this the correct way to get time period of clock of a particular frequency? Please suggest to me some better Verilog code. The code is not ...
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0answers
158 views
ALU implementation in Verilog: how to handle negative numbers?
I am designing a simple ALU with and, add, load operations for 16-bit inputs. This is what I ...
1
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2answers
201 views
Feedback loop in Verilog
I have a problem with writing Verilog HDL code. I want to design a simple PID controller in FPGA I am using Cyclone II family. I want to feedback my output value as an input in a previous stage of ...
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votes
1answer
86 views
To use delay in mealey state machine
I have three states in my mealey machine, when dcsel=0 then it goes to Grayscale state s1,if dcsel=1 then it goes to dot correction state s2,reset=1 then it stays in idle s0.I want to that in ...
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1answer
352 views
Fixed Point Division in verilog for Spartan 6
I am developing a core on Spartan 6 which needs to do divisions like
1/6,2/4 etc... so the values are always between 0 and 1. As I dont need the precision of floating point I am want to use a fixed ...
1
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2answers
129 views
Taking output from FIFO implemented in verilog
I have a big design implemented in Verilog. The design has FIFO as shown in the image below. Due to some reason I have to add a new "Consumer" block shown.
The issue is, this block needs all the ...
0
votes
1answer
110 views
Code Error 9 In Modelsim
When I am trying to do simulation of the following program on Modelsim Altera 10.0d then gives Error : Code Error 9:
** Fatal: (vsim-4) * Memory allocation failure.
Attempting to allocate 131072 ...
2
votes
1answer
167 views
Converting 8 bit bmp to halftone bmp
I am explaining my question in detail now as I am realizing that I did not explain my question well.
I am a beginner in Verilog. To learn the language I am writing some sample applications.
At ...
0
votes
1answer
142 views
What is backdoor memory access?
There is a term in HDL simulation/verification called
"backdoor memory access".
I've heard this a lot of times though I'm
not sure how is this implemented.
Also, there are a few references for this ...
4
votes
3answers
326 views
Generate gate with a parametrized number of inputs
I'm trying to generate a multi-input gate for which the inputs can be selected when the design is elaborated.
Let me give an example to (hopefully) make this more clear:
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