A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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37 views
Best camera and processor for High-Speed Stereo Vision
I'm currently developing a high-speed stereo vision project. So far we've coded all the necessary algorithms and already tested a prototype in matlab (which couldn't get above 30fps). The next step is ...
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2answers
81 views
process timing on FPGA
I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
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53 views
Ideas for a project combining arduino and FPGA [closed]
I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
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0answers
24 views
Should I prefer USB or minitele as audio channel? [closed]
I want to do an audio programming project and I wonder which contact is better for audio if I can choose between minitele and usb? The FPGA I have is Altera DE2.
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2answers
55 views
How to get MicroBlaze running on Papilio Pro
I am new to the FPGA world, and there seems to be gazzilions of boards and FPGA vendors. I just bought the Papilio Pro, which is based on the Spartan 6 LX9, and although I can already bitstream basic ...
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1answer
105 views
Improve my “From NAND to Tetris” ALU in VHDL
I'm following the course From NAND to Tetris, but instead of using the author's software, I'm trying to directly program a Spartan 6 FPGA. I'm now solving the ALU exercise, and ended up writing the ...
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2answers
73 views
Static power of Xilinx FPGA
From the results given by power analyzer, I find that the Xilinx FPGAs always have a high static power consumption no matter what your design is, although it will vary if your design utilize different ...
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39 views
FPGA: 16-port Rx/Tx UART on PCIe card [closed]
I'm designing a PCIe card.
Basically, I have sixteen Rx/Tx lines that I want to expose to the Linux kernel as /dev/ttyS0, /dev/ttyS1, /dev/ttyS2, ... , /dev/ttyS15
Here's some hardware:
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1answer
61 views
VHDL: logical block 'dcm' with type 'DCM_BASE' could not be resolved
I keep getting the following error when I go to implement my design in Xilinx ISE:
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3answers
49 views
Simulating Altera FPGAs with an old version of ModelSim?
I'm hoping to do some development work on Altera FPGAs that will likely be larger than is supported by the free edition of ModelSim. I have an old copy of the full version hanging around (version ...
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1answer
118 views
hold time violation during FPGA post place and route simulation in modelsim
I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below:
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1answer
57 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
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3answers
163 views
Vhdl VGA Problem
I'm doing a fpga project in vhdl for my studies.
I'm displaying a dog on the screen that I try to move. That works well for right, left and up but trying to make the dog go down, it moves in a ...
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0answers
60 views
Using the FT232 with FPGA to program SPI Flash
I want to interface my Xilinx FPGA XC3s250E chip with an external SPI based flash. I am looking at indirect programming where-in the FPGA and the Flash are connected to each other and the FPGA is the ...
0
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1answer
35 views
Xilinx Xpower Analyzer: Expected scope definition in VCD
I use a VCD file to evaluate the power of my design. The VCD is generated using the following command in the testbench file.
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